LSI chips used in recent mobile devices such as mobile terminals are required to execute high-speed processing and to consume little power. These requirements generally are mutually contradictory; if frequency is raised to execute high-speed processing, heat is evolved and power consumption increases. In order to deal with these mutually contradictory requirements, a “substrate biasing technique” has been adopted. This involves applying a potential, which is different from that of a transistor source, to the substrate and controlling substrate potential to thereby reduce leakage when the transistor is cut off. In order to control substrate bias with this substrate biasing technique, a substrate potential for control is separately required in addition to the usual power-supply potential.
An example of a semiconductor integrated circuit device having wiring for supplying a substrate bias that controls substrate potential is disclosed in the specification of Japanese Patent Kokai Publication No. JP-P2001-148464A (see FIG. 1 thereof). This semiconductor integrated circuit device has the structure shown in FIG. 19. Power-supply voltage VDD lines (VDD) 101 and ground voltage VSS lines (GND) 102 are wired alternatingly as a first wiring layer on a semiconductor substrate at regular intervals along the horizontal direction in FIG. 19. Logic cells CA are arranged along the horizontal direction between the power-supply voltage VDD lines 101 and ground voltage VSS lines 102.
A P-channel transistor that operates upon being supplied with power-supply voltage VDD is formed in an area 105 that includes the power-supply voltage VDD line 101 in each logic cell CA. An N-channel transistor that operates upon being supplied with ground voltage VSS is formed in an area 106 that includes the ground voltage VSS line 102 in each logic cell CA.
Furthermore, an n-type substrate potential NSUB line 111 and a p-type substrate potential PSUB line 112, which constitute a pair, are formed as a second wiring layer in the vertical direction in FIG. 19 at right angles to the power-supply voltage VDD lines 101 and ground voltage (VSS) lines 102. Substrate-potential supply cells VSC are placed in the areas in which the logic cells CA are placed. The substrate-potential supply cells VSC are disposed one after another in the vertical direction along the n-type substrate potential NSUB line 111 and p-type substrate potential PSUB line 112, and are supplied with an n-type substrate potential NSUB and a p-type substrate potential PSUB from the n-type substrate potential NSUB line 111 and p-type substrate potential PSUB line 112, respectively. The substrate-potential supply cells VSC apply these potentials to N- and P-type substrates, respectively. Adopting such a structure improves area efficiency.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2001-148464A (FIG. 1)